1. Field of the Invention
The invention relates in general to a method and a circuit for testing a chip, and more particularly, the invention relates to a method and a circuit for testing a chip with the time division function.
2. Description of the Related Art
As semiconductor techniques keep advancing, gate counts in a chip increase rapidly. The system on chip (SOC) has become the leading trend in industry. However, pins provided in a chip to test whether the integrated circuits function normally are not sufficient. Various methods and circuits are proposed to resolve the problems of insufficient test pins.
FIG. 1 shows a conventional internal scan chain structure for testing a chip. In the Internal scan chain structure, the multiplexed flip flops MF1 102, MF2 106, MF3 108 MF4 110 and MF5 104 receive the test pattern in series while clocked by a scan clock signal. When the first scan clock is input, an input terminal SI of the multiplexed flip flop MF1 102 receives a first test pattern. When the second scan clock is input, an input terminal SI of the second multiplexed flip flop MF2 106 receives the first test pattern from an output terminal SO of the multiplexed flip flop MF1 102, and the input terminal SI of the multiplexed flip flop MF1 102 receives the second test pattern.
Accordingly, when the fifth scan clock is input, the multiplexed flip flop MF5 104 receives the first test pattern from the output terminal SO of the multiplexed flip flop MF4 110. Meanwhile, the input terminal SI of the multiplexed flip flop MF4 110 receives the second pattern from the output SO of the multiplexed flip flop MF3 108. The input terminal SI of the multiplexed flip flop MF3 110 receives the third pattern from the output SO of the multiplexed flip flop MF2 106. The input terminal SI of the multiplexed flip flop MF2 106 receives the fourth pattern from the output SO of the multiplexed flip flop MF1 102. The input terminal SI of the multiplexed flip flop MF1 102 receives the fifth pattern.
When the system clock is input, the combinational logic circuit 112 receives the system input signal, the combinational logic circuit 114 receives the fifth test pattern output from the output terminal Q of the multiplexed flip flop MF1 102 and the fourth test pattern output from the output terminal Q of the multiplexed flip flop MF2 106, and the the combinational logic circuit 116 receives the third test pattern output from the output terminal Q of the multiplexed flip flop MF3 108, the second test pattern output from the output terminal Q of the multiplexed flip flop MF4 110, and the first test pattern output from the output terminal Q of the multiplexed flip flop MF5 104 so that the combinational logic circuits 112, 114, 116 can be tested for their circuit functions.
Next, the execution result of the combinational logic circuit 112 is input to the input terminals D of the multiplexed flip flop MF1 102 and the multiplexed flip flop MF2 106. The execution result of the combinational logic circuit 114 is input to the input terminals D of the multiplexed flips flops MF3 108, MF4 110 and MF5 104.
However, when the next scan clock is activated, the output terminal SO of the multiplexed flip flop MF5 104 outputs a first test result. Meanwhile, the output terminal SO of the multiplexed flip flop MF4 110 outputs a second test result to the input terminal SI of the multiplexed flip flop MF5 104. The output terminal SO of the multiplexed flip flop MF3 108 outputs a third test result to the input terminal SI of the multiplexed flip flop MF4 110. The output terminal SO of the multiplexed flip flop MF2 106 outputs a fourth test result to the input terminal SI of the multiplexed flip flop MF3 108. The output terminal SO of the multiplexed flip flop MF1 102 outputs a fifth test result to the input terminal SI of the multiplexed flip flop MF2 106. Accordingly, at the fifth scan clock, the output terminal SO of the multiplexed flip flop MF5 104 outputs the fifth test result.
Thus, the chip is tested with an internal scan chain. The above steps can determine whether the circuit modules in the chip function normally. However, a set of different test patterns have to be input when testing one of the circuit modules. In order to complete the whole test, a large number of test patterns are required.
Furthermore, the test patterns generated for testing the chip have to be changed whenever the circuit modules of the chip change. The launch of the product has to be deferred, and the cost is increased additionally. Further, the multiplexed flip flops occupy a great area in the chip and thus are not economic.
A block diagram of boundary scan in another conventional method for testing a chip is shown in FIG. 2. In FIG. 2, a boundary scan method is used to test logic circuits 202, 204, 206 and 208 with several boundary scan cells 210 arranged therearound.
In FIG. 2, 6 boundary scan cells are arranged around each logic circuit. The boundary scan cells are connected in series, and receive each test pattern serially. When all the boundary scan cells have received the test patterns, the test patterns are sent to all of the logic circuits in parallel. The test results of the logic circuits are received in parallel. The test results are then output one by one in series.
The chip is tested using the boundary scan method. The function of the circuit module of the chip can be tested by the above steps. However, as the test patterns required for all the logic circuits are received or output in series, the time consumption of this operation is significant.
Moreover, the test patterns generated and modified for testing a chip have to be changed as the circuit modules change. The launch of the product has to be deferred. In addition, the multiplexed flip flops occupy a large area of the chip. Again, this is not economic at all.
The relative literature of the boundary scan includes: 1. “Boundary-Scan Test: A practical approach” by Harry Bleeker, Peter Van Den Eijnden, Frans De Jong/Hardcover/Kluwer Acamedic Publishers, January 1993; 2. “The Test Access Port and Boundary-Scan Architecture” by Colin M. Maunder, Rodham Tulloss/Harcover/IEEE Computer Society Press, January 1991.